您的位置: 首页 > 作业答案 > 其他 > LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;ENTITY test IS PORT(F:IN STD_LOGIC;CLK:IN STD_LOGIC;CARRY :IN STD_LOGIC;RIN:IN STD_LOGIC_VECTOR(3 DOWNTO 0);OUT_LOW:OUT STD_LOGIC_VECTOR(3 DOWNTO 0);OUT_HIGH:OUT STD_LOGIC_VECTOR(3 DOWNTO 0));END test;ARCHITECTURE RTL OF test IS SIGNAL F_IN:STD_LOGIC_VECTOR(1 DOWNTO 0);BEGIN PROCESS(CLK,F,CARRY)BEGIN F_IN

LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;ENTITY test IS PORT(F:IN STD_LOGIC;CLK:IN STD_LOGIC;CARRY :IN STD_LOGIC;RIN:IN STD_LOGIC_VECTOR(3 DOWNTO 0);OUT_LOW:OUT STD_LOGIC_VECTOR(3 DOWNTO 0);OUT_HIGH:OUT STD_LOGIC_VECTOR(3 DOWNTO 0));END test;ARCHITECTURE RTL OF test IS SIGNAL F_IN:STD_LOGIC_VECTOR(1 DOWNTO 0);BEGIN PROCESS(CLK,F,CARRY)BEGIN F_IN

分类: 作业答案 • 2022-06-15 21:38:18

问题描述：

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY test IS
PORT(
F:IN STD_LOGIC;
CLK:IN STD_LOGIC;
CARRY :IN STD_LOGIC;
RIN:IN STD_LOGIC_VECTOR(3 DOWNTO 0);
OUT_LOW:OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
OUT_HIGH:OUT STD_LOGIC_VECTOR(3 DOWNTO 0));
END test;
ARCHITECTURE RTL OF test IS
SIGNAL F_IN:STD_LOGIC_VECTOR(1 DOWNTO 0);
BEGIN
PROCESS(CLK,F,CARRY)
BEGIN
F_IN

答

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