verilog 符号扩展Sign-extending the 24-bit signed (two's complement) immediate to 30 bits.将24位的符号数进行符号扩展成30位的,怎么扩展啊?
问题描述：
verilog 符号扩展
Sign-extending the 24-bit signed (two's complement) immediate to 30 bits.将24位的符号数进行符号扩展成30位的,怎么扩展啊?
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