跪求翻译!急忙,有关DSP

跪求翻译!急忙,有关DSP
Example 7–54. Loading BRC Before Executing a New Repeat-Block Loop
(a)
STM #lk,BRC ; There is no latency when BRC is
RPTB endloop–1 ; loaded via STM before a new RPTB
... ; loop.
endloop:
(b)
MVDK count,BRC ; There is no latency when BRC is
RPTBD endloop–1 ; loaded using MVDK before a new
... ; RPTB loop
endloop:
(c)
STLM A,BRC ; There is a 1 cycle latency when
NOP ; BRC is loaded using an STLM
RPTB endloop–1 ; instruction.
...
endloop:
(d)
POPM BRC ; There is a 1 cycle latency when
NOP ; BRC is loaded using a POPM
RPTBD endloop–1 ; instruction.
...
endloop:
In a repeat-block loop, BRC is decremented when the last instruction in the
loop is in the decode stage of the pipeline. However, the SRCCD instruction
writes the BRC’s contents in the execute stage of the pipeline. This can result
in an incorrect BRC value written by the SRCCD instruction. The pipeline conflict
can be avoided by placing the SRCCD instruction at least three instruction
words from the bottom of the loop, as shown in Example 7–55 and
Example 7–56.
Example 7–55. SRCCD Instruction With No Latency
RPTB endloop–1
...
SRCCD *AR3, ALEQ ; Placing the SRCCD instruction in
; this position ensures that current
; value of BRC will be written
; to memory.
ADD *AR1+,A
SUB *AR2–,A
STH A, *AR1+
endloop
麻烦哪位大侠帮忙翻译下，翻译错误一些没关系，但是要和原本的的格式对应一点，看起来漂亮一点就行