vHdl程序分析 (5 DOWNTO 0); 表示什么ARCHITECTURE Behavioral OF FIFO ISTYPE fifo_array IS ARRAY(0 TO 4095) OF STD_LOGIC_VECTOR(9 DOWNTO 0); SIGNAL fifo_memory :fifo_array; SIGNAL full_flag :STD_LOGIC; SIGNAL empty_flag :STD_LOGIC; SIGNAL read_addr :STD_LOGIC_VECTOR(5 DOWNTO 0); SIGNAL write_addr :STD_LOGIC_VECTOR(5 DOWNTO 0); SIGNAL counter :STD_LOGIC_VECTOR(5 DOWNTO 0);

vHdl程序分析 (5 DOWNTO 0); 表示什么
ARCHITECTURE Behavioral OF FIFO IS
TYPE fifo_array IS ARRAY(0 TO 4095) OF STD_LOGIC_VECTOR(9 DOWNTO 0);
SIGNAL fifo_memory :fifo_array;
SIGNAL full_flag :STD_LOGIC;
SIGNAL empty_flag :STD_LOGIC;
SIGNAL read_addr :STD_LOGIC_VECTOR(5 DOWNTO 0);
SIGNAL write_addr :STD_LOGIC_VECTOR(5 DOWNTO 0);
SIGNAL counter :STD_LOGIC_VECTOR(5 DOWNTO 0);