Error (10228):Verilog HDL error at top.v(1):module "top" cannot be declared more than once

分类: 作业答案 • 2021-12-19 22:55:04

问题描述：

Error (10228):Verilog HDL error at top.v(1):module "top" cannot be declared more than once
晕

答

貌似叫top 的module 被命名了不知一次